Sometimes good ideas take a while to catch on in engineering practice. The use of in-line assertions to document assumptions and check for problems in RTL code is one such idea. Long ago proposed for ...

This repository captures my learning journey through the RISC-V Reference SoC Tapeout Program organized by VSD & IIT Gandhinagar, covering Verilog RTL design, synthesis, labs, and optimization ...

A multiplexer (MUX) is a fundamental building block in digital electronics used to select one of many input signals and forward the selected input to a single output line. This functionality makes it ...

Breathing LEDs are an attractive adornment on many electronic devices. These days they’re typically controlled by software but of course there were fading effects back in the days of analog too.

Never in my wildest dreams did I think that the Verilog hardware description language (HDL) would spawn an industry and be a fixture of electronics design for more than 15 years. HDLs were a ...

The Ease 5.2 is a design-entry environment for VHDL, Verilog, and mixed-language FPGA and ASIC designs. Synthesis and simulation independence enables users to select their favorite tools while setting ...

You probably couldn’t write a decent novel if you’d never read a novel. Learning to do something often involves studying what other people did before you. One problem with trying to learn new ...

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.