GitHub

Mazen-14/UART-USING-VERILOG

This repository contains the Verilog implementation and testbench for a Universal Asynchronous Receiver Transmitter (UART) module. The project includes the architecture, Verilog code, and simulation ...
GitHub

UART Transceiver Using FPGA

This repository contains Verilog code for implementing a UART (Universal Asynchronous Receiver Transmitter) communication protocol in an FPGA. UART is commonly used for serial communication between ...
IEEE

FPGA based UART Design: Simulation, Synthesis & System Verilog functional verification

Abstract: The UART is a communication protocol that operates on serial data transmission (sending information bit-by-bit) between different modules asynchronously. As the number of devices increases, ...
IEEE

128-bit Asynchronous Gray Code FIFO using Verilog HDL

Abstract: This paper presents the design and implementation of a 128-bit Asynchronous Gray Code FIFO using Verilog HDL. The FIFO is designed for bidirectional transfer of data between different clock ...