Design-Reuse

OptNgn Delivers 2D-FFT FPGA Library Elements for use in Imaging and DSP applications

Portland, Oregon -- October 1, 2010-- At processing rates of up to 306 complex mega pixels per second (Mpps), the new OptNgn 2DFFT FPGA library elements are the perfect choice for inexpensive, low ...
EDN

AccelChip IP-Explorer removes trial and error of DSP algorithm optimization

AccelChip, provider of IP and software for MATLAB and Simulink DSP algorithms announced technology it says provides unparalleled automation for DSP applications in FPGAs and ASICs. AccelChip DSP ...
EDN

A Prototype Lab Box with DSK’C6711/13 for Rapid DSP Algorithm Development

Rapid prototyping is a new approach in Digital Signal Processing systems development. With the advent of Matlab's Real Time Workshop (RTW) it is now possible to compile, load, and execute graphically ...
Design-Reuse

Synopsys System Studio Speeds DSP Algorithm Development With New Matrix Data-Type Support

Enhances Model Authoring Efficiency and Simulation Performance Utilizing Multicore Capabilities MOUNTAIN VIEW, Calif., March 3, 2010 -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP ...