GitHub

soumya-2911/UART-Verilog

This repository contains the Verilog implementation and simulation of a Universal Asynchronous Receiver-Transmitter (UART) protocol using Quartus. The project includes separate modules for ...
GitHub

Sachin-g2/verilog_uart_tx

This is a basic UART to AXI Stream IP core, written in Verilog with testbenches. The AXI4-Stream UART Transmitter (uart_tx) is designed to serialize parallel data received via an AXI4-Stream interface ...
IEEE

FPGA based UART Design: Simulation, Synthesis & System Verilog functional verification

Abstract: The UART is a communication protocol that operates on serial data transmission (sending information bit-by-bit) between different modules asynchronously. As the number of devices increases, ...
IEEE

128-bit Asynchronous Gray Code FIFO using Verilog HDL

Abstract: This paper presents the design and implementation of a 128-bit Asynchronous Gray Code FIFO using Verilog HDL. The FIFO is designed for bidirectional transfer of data between different clock ...
Design-Reuse

Capturing a UART Design in MyHDL & Testing It in an FPGA

The universal asynchronous receiver/transmitter (UART) is an old friend to embedded systems engineers. It's probably the first communications protocol that we learn in college. In this article, we ...