Designed a 16-bit array multiplier using carry save adders and drawing layout in Cadence. Improved performance of multiplier by pipelining multiplier using flip flops and latches.
Abstract: The proposed work focuses on the layout design of a JK flip-flop aimed at achieving lower power consumption through the innovative application of the Gate Diffusion Input (GDI) technique.
SAN JOSE, Calif. & SANTA CLARA, Calif.-- June 3, 2014-- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design automation, and Intel Corporation, a world leader in computing ...
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