Semiconductor Engineering

Smart Handling Of Reset Domain Crossings To Non-Resettable Flip-Flops

A flexible approach to RDC verification allows skip-depth to be defined on a per-path basis, with different Tx resets and Rx clocks.
IEEE

Top-down design process for gate-level combinational logic design

Abstract: A pedagogical process for designing gate-level combinational logic circuits is described. The process can be used for either combinational logic circuits or the combinational logic sections ...
EDN

Best design practices for DFT

SoC sub-components (IPs) generally come from various sources – internal and external – and with that it has become necessary that designers ensure the RTL is testable. If the RTL has testability ...
IEEE

Combinational logic design in Synthetic Biology

Abstract: Combinational logic circuits are a fundamental building block in today's digital electronics. Combinational logic representations are highly amenable to various levels of abstraction, and ...
GitHub

This repository contains four laboratory assignments covering combinational circuits, sequential logic with Verilog, FPGA implementation, and memory systems.

Simplify and implement a circuit with inputs A1, A0, B1, B0 and outputs X, Y, Z using only 74LS ICs in Logisim. Learn Boolean algebra simplification and basic gate usage. Lab 2: Multiplexers, Decoders ...
EDN

10 design issues to avoid during clock domain crossing

The modern ASIC consists of millions of gates and billions of transistors that often can be operating in several domains having different voltages and clock frequencies. To avoid data loss, designers ...
Design-Reuse

Scan Chains: PnR Outlook

At times physical design engineers find it difficult to relate with the additional timing modes introduced in PnR due to DFT insertion. These additional timing modes and related issues could be ...